1. Field of the Invention
The present invention relates to a method for controlling memory data access, and more particularly, to an apparatus and related method for adjusting pulse widths to generate a control signal for controlling a switch module on a data transmission path in a memory by detecting an operation voltage of the memory.
2. Description of the Prior Art
In general, before accessing a sum of data, a microprocessor needs to send an input instruction signal (e.g. a data read instruction signal or a data write instruction signal) to a memory (e.g. a DRAM {Dynamic Random Access Memory}) for informing the memory a data access operation will be performed. It is also necessary for the microprocessor to send an input address signal corresponding to the sum of data to the memory such that the sum of data can be accessed correctly according to the input address signal. Before the sum of data is accessed, a decoder performs a decoding operation upon the input address signal and the input instruction signal simultaneously to output a control signal for controlling a turn-on period of a switch module in the memory so data can be accessed through the switch module. For example, data in memory cells within a specific memory bank in the memory can be accessed through the switch module when the switch module is turned on. Additionally, since the input instruction signal or the input address signal is usually inputted into the memory in the form of a voltage signal, the memory needs to use corresponding pins to receive the above-mentioned voltage signals. The voltage signal has a high voltage level (e.g. five Volts) or a low voltage level (e.g. zero Volts). An operating clock signal (i.e. a memory clock) is also necessary for the memory. The operating clock signal is utilized for estimating the voltage level corresponding to the input address signal in order to obtain information of the input address signal for performing a data access operation for the memory.
In practice, however, if an operation voltage of the memory arrives at a higher voltage level, the pulse width of the input instruction signal is shortened and the turn-on period of the switch module is also decreased. This reduces a period for accessing data. Otherwise, if the operation voltage of the memory arrives at a lower voltage level, the pulse width of the input instruction signal is extended and thus a decoder corresponding to the switch module in the memory may not operate properly. Please refer to FIG. 1. FIG. 1 is a timing diagram illustrating a prior art scheme for controlling the switch module in the memory for accessing data. The switch module is controlled by a signal CTRL to be turned on or turned off. As shown in FIG. 1, a signal CLK represents an operating clock signal of the memory, and a signal ADDR represents the input address signal. A signal COM1 (e.g. a data read instruction signal or a data write instruction signal) represents the input instruction signal when the operation voltage of the memory is operated at a normal voltage level. A data read operation or data write operation is performed when the input instruction signal COM1 remains at a high voltage level (e.g. the pulse width PW1 of the input instruction signal COM1). A signal COM2 is an example of the input instruction signal for the operation voltage of the memory being operated at a higher voltage level. The pulse width of the control signal is involved due to the pulse width PW2 of the input instruction signal COM2, and thus the pulse width of the control signal becomes shorter than the pulse width PWCTRL of the control signal CTRL for the operation voltage of the memory being operated at a normal voltage level. This reduces the turn-on period of the switch module and a period for accessing data becomes shorter. On the other hand, a signal COM3 is an example of the input instruction signal for the operation voltage of the memory being operated at a lower voltage level. The decoder is involved due to the pulse width PW3 of the input instruction signal COM3 and may not operate properly when performing a decoding operation. The reason is that the pulse width PW3 may be too long to exceed a rising edge or a falling edge of the pulse width PWADDR of the input address signal ADDR.